Advances in the field of semiconductor integrated circuits (ICs) have brought about higher levels of integration. Accordingly, semiconductor manufacturing process advancements are driving the corresponding geometric dimensions of semiconductor devices to decreasingly smaller values. 10 micrometer (μm) gate lengths, for example, were common in the 1970's, but continuously advancing semiconductor manufacturing processes have reduced gate lengths to well below 100 nanometers (nm) for deep sub-micron integrated circuit (IC) design.
One key challenge presented by deep sub-micron design is the adjustment of the various semiconductor processing steps required to implement devices within a silicon die so as to obtain acceptable yield and manufacturability. Such process adjustments, however, may lead to significant performance deviations between simulated devices that are designed and characterized within a design/simulation environment and the corresponding physical devices that are implemented within a semiconductor die.
Operating parameters, such as transistor threshold voltage, leakage current, and saturation current, for example, may be so affected by the process variations that performance of the devices no longer corresponds to design specifications previously verified within the design/simulation environment. As a result, process variations that optimize yield and manufacturability may also contribute to detrimental effects on device performance, such as increased leakage current, reduced threshold voltage, and/or increased saturation current.
As geometric features of the deep sub-micron devices continue to shrink, scaling, implant, and annealing process variations invoke increasingly significant device performance degradations. Reducing the effects of such process-based performance variation has conventionally been implemented either by specifically designing the semiconductor processing steps to minimize process-induced performance degradation, or by changing the equipment used during one or more of the semiconductor processing steps.
Equipment changes utilized to reduce semiconductor device variability during semiconductor processing include, for example, the switch from batch to serial high-current implanters and the switch from radiative to conductive rapid thermal processing. Devices exhibiting 45 nm gate lengths will likely further require a switch to iso-scan, medium current implanters and milli-second annealing processes. Mitigation of process-based, performance variation, however, is often cost prohibitive because such mitigation efforts involve substantial time and money investments before any benefits may be obtained.